1. Field of the Invention
The present invention generally relates to a memory device including a delay locked loop (hereinafter, referred to as “DLL”), and more specifically, to a memory device including a DLL which is configured to minimize the skew an external clock and a DQS (or a DQ) after locking by compensating errors generated from process errors by a delay ratio of a replica delay model and from temperature or voltage change.
2. Description of the Prior Art
In general, a DLL is a circuit for controlling timing of data outputted externally from a DRAM by using an externally inputted external clock of the DRAM. In order to transmit data to a chipset without errors, the DRAM is required to be synchronized with the chipset at the same clock.
That is, when an externally inputted clock is inputted into the inside of the DRAM, a phase is delayed by logic circuits such as an clock input buffer, line loading and a data output buffer, and a phase of an external clock becomes different from that of an internal clock. As a result, the DLL is used to compensate the difference.
In this way, the DLL compensates a phase (clock skew) delayed by an internal circuit of the DRAM, and sets the timing of an externally inputted clock to be the same as when data sensed at the core of the DRAM are outputted from a data output buffer on a basis of an external clock so that the phase of data from the inside to the outside may not become different from that of the clock.
FIG. 1 is a block diagram illustrating a general memory device including a DLL.
The memory device includes an input clock buffer 2, a DLL 4, an output clock buffer 6 and an output control unit 8.
The input clock buffer 2 buffers an externally inputted external clock CLKEXT, and outputs an internal clock CLKIN.
The DLL 4 includes a phase detector 10, a delay line 11, a delay line controller 12 and a replica delay model 13. The phase detector 10 compares a phase of an internal clock CLKIN outputted from the input clock buffer 2 with that of a feedback clock FBCLK fed back through an internal circuit. The delay line 11 delays a phase of the internal clock CLKIN. The delay line controller 12 controls a delay ratio of the delay line 11 in response to a phase detecting signal outputted from the phase detector 10. The replica delay model 13 models delay factors of the input clock buffer 2 and other delay factors until an output clock CLKOUT outputted from the delay line 11 are outputted to the outside of the chip.
The phase detector 10 compares the internal clock CLKIN with the phase of the feedback clock FBCLK. That is, two clocks are compared on real time in order to synchronize a phase of the external clock CLKEXT and that a DQS.
The phase detector 10 provides comparison information to the delay line controller 12 (for example, a shift register array), and regulates a delay ratio of the delay line 11, thereby decreasing a phase difference of the two clocks.
The delay line 11 is controlled by the phase detector 10, and forms a delay path for determining a phase delay ratio. The delay line 11 includes a plurality of unit delay cells which are connected in series. A signal for controlling each unit delay signal corresponds one by one to a signal outputted from the delay line controller 12.
The delay line controller 12 includes a bidirectional shift register for setting a logic circuit for setting an input path of the delay line 11 and locations of paths. Here, the shift register is configured to set the initial maximum/minimum delay time.
The delay line controller 12 outputs a signal for controlling the delay line 11 in response to a state detected by the phase detector 10. The delay line controller 12 generates a shift left signal DELUP to increase a delay ratio at the lead state, and a shift right signal DELDN at the lag state. At the lock state, the delay line controller 12 does not generate a shift signal but outputs a synchronization state signal LOCK.
The replica delay model 13 shrinks, simplifies or uses an internal circuit as it is except the DLL from input to output of the external clock CLKEXT. The exact delay factors determine a skew value of performances of the DLL.
The output clock buffer 6 buffers the output clock CLKOUT outputted from the delay line 11.
The output control unit 8 generates a DQS by using a clock CLKINTP outputted from the output clock buffer 6.
FIG. 2 is a detailed block diagram illustrating the phase detector 10 of FIG. 1.
The phase detector 10 includes phase detecting units 16 and 18, and a delay unit 20. Here, the delay unit 20 includes a unit delay cell.
The first phase detecting unit 16 compares a phase of the internal clock CLKIN with that of the feedback clock FBCLK. When a rising edge of the feedback clock FBCLK is in a low pulse of the internal clock CLKIN, that is, the rising edge of the feedback clock FBCLK leads that of the internal clock CLKIN, an output signal DET1 of the first phase detecting unit 16 becomes at a low level. However, when the rising edge of the feedback clock FBCLK lags that of the internal clock CLKIN, the output signal DET1 of the first phase detecting unit 16 becomes at a high level.
The second phase detecting unit 18 compares a phase of the internal clock CLKIN with that of a delay feedback clock FBCLKD delayed by the delay unit 20. When a rising edge of the delay feedback clock FBCLKD is in a low pulse of the internal clock CLKIN, that is, the rising edge of the delay feedback clock FBCLKD leads that of the internal clock CLKIN, an output signal DET2 of the second phase detecting unit 18 becomes at a low level. However, when the rising edge of the delay feedback clock FBCLKD lags that of the internal clock CLKIN, the output signal DET2 of the second phase detecting unit 18 becomes at a high level.
FIGS. 3a to 3d are timing diagrams illustrating the operation of the phase detector 10 of FIG. 2.
FIG. 3 is a timing diagram when the rising edges of the feedback clock FBCLK and the delay feedback clock signal FBCLKD lag that of the internal clock CLKIN. As a result, the output signals DET1 and DET2 of the first phase detecting unit 16 and the second phase detecting unit 18 in the phase detector 10 of FIG. 2 become all at the high level, and the delay line controller 12 generates a delay up signal DELUP for increasing a delay ratio of the delay line 11.
As shown in FIG. 3b, the feedback clock FBCLK and the delay feedback clock FBCLKD are delayed, the rising edge of the feedback clock FBCLK lags that of the internal clock CLKIN, and the rising edge of the delay feedback clock FBCLKD leads that of the internal clock CLKIN. As a result, the output signal DET1 of the first phase detecting unit 16 becomes at the high level, and the output signal DET2 of the second phase detecting unit 18 transits from the high level to a low level. Then, the delay line controller 12 generates the delay up signal DELUP for increasing a delay ratio of the delay line 11.
As shown in FIG. 3c, the feedback clock FBCLK and the delay feedback clock FBCLKD are delayed, and the rising edges of the feedback clock FBCLK and the delay feedback clock signal FBCLKD lead that of the internal clock CLKIN. As a result, the output signals DET1 and DET2 of the first phase detecting unit 16 and the second phase detecting unit 18 become all at the low level. Then, the delay line controller 12 generates the delay up signal DELUP for increasing a delay ratio of the delay line 11.
As shown in FIG. 3d, the feedback clock FBCLK and the delay feedback clock FBCLKD are delayed, the rising edge of the feedback clock FBCLK leads that of the internal clock CLKIN, and the rising edge of the delay feedback clock FBCLKD lags that of the internal clock CLKIN. As a result, the output signal DET1 of the first phase detecting unit 16 becomes at the low level, and the output signal DET2 of the second phase detecting unit 18 transits from the low level to the high level. Then, the rising edge of the internal clock CLKIN becomes closer to that of the feedback clock FBCLK at a less than predetermined interval, which results in a lock state. Here, whether a delay up signal DELUP or a delay down signal DELDN outputted from the delay line controller 12 is generated only by the output signal DET1 from the first phase detecting unit 16 is determined. That is, the delay up signal DELUP is outputted when the output signal DET1 from the first phase detecting unit 16 is at the low level, and the delay down signal DELDN is outputted when the output signal DET1 is at the high level.
FIG. 4 is a detailed block diagram illustrating a delay line 11 of FIG. 1.
The delay line 11 includes a plurality of unit delay cells 22 which are connected in series and whose delay paths are set in response to the output signals DELUP and DELDN from the delay line controller 12.
If the delay up signal DELUP is outputted from the delay line controller 12, the delay path of the delay line 11 is set as shown in A of FIG. 4, and the delay ratio increases. If the delay down signal DELDN is outputted, the delay path of the delay line 11 is set as shown in B of FIG. 4, and the delay ratio decreases.
FIGS. 5a and 5b are timing diagrams illustrating the lock state of the memory device of FIG. 1.
FIG. 5a is a timing diagram illustrating the ideal case. The rising edge of the internal clock CLKIN becomes identical with that of the feedback clock FBCLK delayed by a delay time D1 of the replica delay model 13 at the lock state. Here, the rising edge of the external clock CLKEXT is identical with that of the DQS obtained by delaying the output clock CLKOUT of the DLL for a delay time D2 by the output clock buffer 6 and the output control unit 8.
FIG. 5b is a timing diagram when the rising edge of the DQS is not identical with that of the external clock signal CLKEXT.
Referring to FIG. 5b, the feedback clock FBCLK delayed by the delay time D1 of the replica delay model 13 is identical with the rising edge of the internal clock CLKIN at the lock state. When a delay time D3 of the output clock CLKOUT of the DLL 4 so that the rising edge of the DQS may be identical with that of the external clock signal CLKEXT is not identical with the delay time D2 of the output clock CLKOUT of the DLL 4 delayed by the output clock buffer 6 and the output control unit 8, the rising edge of the external clock signal CLKEXT is not identical with that of the DQS.
Accordingly, it is impossible to regulate the delay ratio of the replica delay model 13 in order to identify the actual delay time D2 with the ideal delay time D3 in the conventional memory device. As a result, the skew between the external clock CLKEXT and the DQS (or DQ) cannot be reduced.